This board contains the 2nd IF amplifier (9-MHz), AGC detector, and digital AGC.
The original IF Amplifier Board for the Express Receiver used two Analog Devices AD603 low noise, variable gain amplifiers. However, after building three boards and testing stages individually and in cascade, I could not achieve the gain control range and linearity expected based on the AD603 specifications. My objective is for an AGC range of at least 80-dB.
Therefore, I decided to abandon the AD603 design and return to the classic Wes Hayward W7ZOI and Jeff Damm WA7MLH, “Hybrid Cascode General Purpose AGC IF Amplifier,” QST pp. 30-33, DEC, 2007. I have replaced the AGC detector and control circuitry with the AD8307 and PIC33F from the AD603 based IF Board design. I won’t cover the operation of the Hybrid Cascode IF amplifier stages here as that is well covered in the original article, but focus on my implementation and results.
Three hybrid cascode stages are used consisting of Q1 – Q6. The linear gain control range of the three stages is -45- to +45-dB, exceeding my objective of 80-dB.
I replaced the input matching L network in the original hybrid cascode design with a broadband transformer. The transformer provides a 1:64 impedance transformation of the 50Ω input impedance to the 3.3KΩ Q2 gate resistance. This provides a well defined, broadband 50Ω input impedance for the IF filters in the previous stage, and eliminates the need for tuning of the IF amplifier input.
Output of the third hybrid cascode stage is transformer coupled to a differential pair of PNP transistors consisting of Q7 and Q8.
Q7 drives an Analog Devices AD8307 Logarithmic Amplifier that implements the AGC detector function. The AD8307 provides an output voltage scaled to 0.25mV/dB. This voltage varies from 0.25 V with an input signal level of −74 dBm up to 2.5 V for an input signal level of +16 dBm, a dynamic range of 90 dB. The target output level for the IF amplifier is ~-35-dBm to provide optimal drive for the TUF-1 diode ring mixer product detector in the following stage. This target output level results in an AD8307 output voltage of ~1.36 volts, which is in the middle of the AD8307 voltage output range, ensuring linear a response.
The measured AGC Characteristic shows the resulting linearity achieved.
Q8 drives the product detector in the Product Detector, BFO, and AF Amplifier board via a 50Ω termination.
The brains of the digital AGC is the Microchip dsPIC33FJ12GP201 high performance 16-bit digital signal controller that performs the following functions on the IF amplifier board.
- Reads IF signal level from the AD8307 every 1ms
- Updates the Automatic Gain Control (AGC) voltage every 1ms
- Sets AGC SLOW, FAST, and MANUAL operation
- Provides signal strength readings (AGC voltage)
- Manages Slave I2C Communications
The dsPIC33F supports up to 10 channels of 10-bit or 12-bit analog to digital conversion (ADC). A single ADC channel, configured for 12 bit operation, is used to measure signal strength at the output of the IF amplifier. A second ADC channel input is made available via J4 for future use.
One DAC of the MCP4822 dual 12-Bit voltage output DAC U3 provides the AGC control voltage for the hybrid cascode IF amplifier, the second DAC output is made available via J4 for future use. A second MCP4822 U4, not populated on the board at this time, is included to support future functionality. Both DAC outputs from U4 are available via J4.
The dsPIC33F is a 3.3V device, however, the I2C SDA1 and SCL1 pins (port pins RB9 & RB8, respectively) are 5V tolerant and can be configured for Open Drain operation, allowing direct connection to the Express Receiver 5V I2C Bus.
U2 is a Microchip dsPIC33FJ12GP201 high performance 16-bit digital signal controller, Mouser PN 579-DSPICJ12GP201ISO.
U5, U6 and U7 implement the power regulation chain providing regulated 9V, 5V and 3.3V, respectively. The hybrid cascode amplifier requires 9V, the AD8307 5V, and the dsPIC33F and MCP4822 3.3V.
U5 is a LM2940IMP-9.0 low drop out, 1 amp, 9 volt regulator in an SOT223 SMD package, Digikey PN LM2940IMP-10/NOPBTR-ND.
U6 is a LM2940IMP-5.0 low drop out, 1 amp, 5 volt regulator in an SOT223 SMD package, Digikey PN LM2940IMP-5.0/N0PBCT-ND.
U7 is a LM3940IMPX-3.3 low drop out, 1 amp, 3.3 volt regulator in an SOT223 SMD package, Digikey PN LM3940IMPX-3.3/N0PBCT-ND.
Q1, Q3 and Q5 are are 2N3904 general purpose NPN transistors in SMD SOT-23 package, Mouser 512-MMBT3904.
Q2, Q4 and Q6 are J310 N-channel JFET RF transistors in SMD SOT-23 package, Mouser 512-MMBFJ310.
Q7, Q8 and Q9 are 2N3906 general purpose PNP transistors in SMD SOT-23 package, Mouser 512-MMBT3906.
D1 through D3 are 1N4148 general purpose diodes in SMD SOD-123 package, Mouser PN 621-1N4148W-F.
D4 is clear green LED in SMD 1206 package, Mouser 645-598-8270-107F.
L1 and L2 are through hole mounted 47μH RF chokes, Mouser 542-77F470-RC.
Y1 is an Abracon 40-MHz standard clock oscillator, Mouser PN 815-ACHL-40-EK.
T1 and T2 are wound on Amidon Corp FT-37-43 ferrite cores. Refer to the schematic for turns and wire gauge information.
All 0.1μF, 0.01μF and 0.001μF capacitors are 1206 style chip capacitors.
C22 and C29 are 33μF 10%, 16V tantalum capacitor in a size D SMD package, Mouser PN 80-T491A336K010.
C24 & C26 are 33μF 10%, 10V tantalum capacitor in a 1206 SMD package, Mouser PN 80-T495D336K016.
C21, C23 & C25 are 0.47μF 10%, 25V tantalum capacitors in a size A SMD package, Mouser PN 80-T491A474K025.
Resistors are 1/8W 5% SMD 1206 style chip resistors; except R18 and R22 (51Ω) which is 1/8W 1% SMD 1206 style chip resistor.
J1 & J2 are female machined pin breakaway headers from Sparkfun, PN PRT-00743. Refer to the RF Band Pass Filter page for additional information.
J5 is a right-angle breakaway header that provides access for in-circuit programming of U2 using the PICkit 3 when the IF Amplifier Hybrid Cascode Board is installed vertically in the Express Receiver. Sparkfun, PN PRT-00553.
Refer to the RF Band Pass Filter page for information on the connectors J3, J4, J6 (not used) and J7.
The IF amplifier PCB was partitioned into a digital and power regulation section, and an analog section, with partitioned ground planes interconnected at a single point on the board.
There were a couple of errors in the original boards that appear in the photos above that have been corrected in the final versions. The ExpressPCB .pcb file for the board is here: IF Amplifier Hybrid Cascode_v2
Software for the dsPIC33FJ12GP201 is in three files as follows:
Initialization.c performs initialization and configuration of dsPIC33F peripherals and the MCP4822 DAC.
MCP4822.c provides the software driver to write data to the MCP4822 DAC.
main.c implements a fairly simple AGC algorithm that runs every millisecond in the Timer1 interrupt service routine, and an I2C interrupt service routine to handle commands and data requests received via the Express Receiver I2C bus.
Valid commands to the IF Board are as follows:
- AGC Slow Mode – put AGC in slow recovery mode
- AGC Fast Mode – put AGC in fast recovery mode
- AGC Manual Mode – put AGC in manual mode with specified IF gain setting
- AGC Slow Recovery Rate Set (not currently implemented)
- AGC Fast Recovery Rate Set (not currently implemented)
AGC Slow recovery time is currently fixed at ~2 seconds, while fast recovery time is fixed at ~one tenth of a second.
The AGC Manual Mode command includes an index to one of 19 levels corresponding to IF gain settings of -45-dB to +45-dB in 5-dB steps. The manual IF gain is set via the keypad function Manual IF Gain Set.
The S Meter reading is updated every 1ms when the AGC is in either Slow or Fast mode based on the AGC voltage generated from the AGC loop running in the Timer1 interrupt service routine. The Main Display and Control Board periodically requests an S Meter reading from the IF Board to update the S Meter display. S Meter readings are not generated when AGC is in Manual mode, in this mode the S Meter displays the manual IF gain setting in dB.
The IF Board defaults to AGC Slow mode upon start up, and will happily run in this mode if operated standalone. If the IF Board was to be used in a standalone fashion, Slow and Fast AGC selection could be implemented by connecting a switch to J6 with a pull up resistor on RB15 and appropriate software changes.
© 2014 – 2016 Rod Gatehouse AD5GH